Abstract:
The authors describe an experimental 16-kb nonvolatile memory using two memory cells per bit with one transistor and one ferroelectric capacitor per memory cell. The RAM ...Show MoreMetadata
First Page of the Article
Abstract:
The authors describe an experimental 16-kb nonvolatile memory using two memory cells per bit with one transistor and one ferroelectric capacitor per memory cell. The RAM measures 5 mm*7 mm with 462 mu m/sup 2/ per bit. It is built in a 2- mu m CMOS n-well process and has a chip-enable access time of 200 ns. The authors also demonstrate a bit-parallel architecture in which the common plate of the capacitors runs parallel to the bit lines and connects all bits in a given column. The typical characteristics of the device are given.<>
Published in: IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers
Date of Conference: 15-17 February 1989
Date Added to IEEE Xplore: 06 August 2002
First Page of the Article
