200 MHz 16-bit BiCMOS signal processor

A 200-MHz, 600-MOPS, 16-bit, super-high-speed fixed-point BiCMOS DSP (digital signal processor) has been developed for video signal processing, including discrete cosine transforms (DCTs) for picture coding. A block diagram is shown of the processor, which consists of a 16-bit binary adder, a 16-bit*16-bit redundant binary multiplier (RB-MPY), and a 35-digit RB accumulator (RB-ACC). The RB-MPY is constructed with an RB adder tree and two dynamic pipeline registers. The RB-ACC is specially integrated to produce a high-speed RB convolver. Two input registers, in which B-to-RB conversion takes place, and a 35-bit RB-to-B converter, are also provided. A 0.8 mu m BiCMOS and triple-layer Al interconnection have been developed for the processors. Speed improvement over commercially available 1.3- mu m processes by a factor of 1.7 has been achieved by employing both W-polycide for low resistance MOSFET gates and TiSi/sub x/ for sources and drains and by shrinking device size. The device's signal processing capabilities are summarized.<
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