A low power signal-swing suppressing strategy using time-multiplexed differential data-transfer (TMD) scheme

This paper presents a signal-swing suppressing strategy which uses a time-multiplexed differential data-transfer (TMD) scheme, featuring shared complementary wires between adjacent signal-bits. TMD can be exploited to reduce the signal voltage-swing and to realize a charge-recycling bus (CRB) architecture. This enables a dramatic power reduction without the throughput-loss due to the time-multiplexing, while maintaining the same number of signal wires compared to a single signal line (SSL) scheme. This is because the differential transfer scheme inherently has over 4-times higher capability in terms of throughput and noise tolerance compared to SSL. To demonstrate the effectiveness of TMD and TMD with CRB (TM-CRB), power consumption comparisons were made between SSL, the parallel architecture (parallelism), TMD, and TM-CRB. For all measurements, the same throughput conditions were used based on the simulated and measured data of the 0.5 /spl mu/m CMOS devices. This paper shows why TMD and TM-CRB can reduce the power dissipation on heavily loaded data lines to less than 1/3 and 1/20, respectively, compared to the parallelism, while reducing the number of signal wires by half.