A 1,000,000 transistor microprocessor

The authors describe a 1,000,000-transistor single-chip microprocessor which uses RISC (reduced-instruction-set-computer) design techniques, parallel instruction execution, a 64-bit data bus, and supercomputer architectural concepts. To achieve balanced performance, one-third of the chip area is devoted to integer instructions, including a 32-bit integer core, paging unit, and bus unit; one-third is devoted to floating-point instructions, including the floating-point control unit, add and multiply units, and a 3-D graphics unit; and one-third to three instruction and data caches. The integer unit and floating-point add and multiply units can execute in parallel to provide up to three operations per clock. Bringing the instruction and data caches on-chip allows an aggregate data rate of 1.2 Gbytes/s, which is necessary to support the parallel execution. At 50 MHz, the device achieves 105000 dhrystones and 21 MFLOPs (million floating-point operations per second) in the double-precision Linpack inner loop. The chip size is 10 mm*15 mm using a 1- mu m double-metal CHMOS process.<
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