A design of full-CMOS VDSL2 receiver in 0.25μm CMOS process

This paper presents a full-CMOS single-chip Receiver PHY IC for VDSL2 systems. In the receiver part, the low-pass filter, VGA, and ADC is designed to have a wide dynamic range and gain control range because the signal from the VDSL2 line is variable depending on the distance. This chip is fabricated with 0.25 mum CMOS technology, and the die area is 5 mm times 5 mm. The power consumption is 250 mW at 2.5 V supply voltage in Rx mode.