A high-linearity sampling technique for switched-current circuits

Currently the dynamic range of switched-current circuits is much lower than that of switched-capacitor circuits. To address this problem, a current-mode sample-and-hold technique based on zero-voltage switching is presented. The technique avoids signal-dependent charge injection, thereby significantly increasing the sampler's linearity. A sample-and-hold, based on the technique, was implemented using a 1.2 /spl mu/m CMOS process and achieved 13-b linearity at sampling rates exceeding 50 MSamples/s, while dissipating only 5.3 mW from a 3.3 V supply.