Erratum to “Simulation Study on the Effect of Multiple Node Charge Collection on Error Cross-Section in CMOS Sequential Logic”

In the above titled paper (ibid., vol. 55, no. 6, pp. 3136-3140, Dec 08), Figs. 1, 2, 4, 5, 7, and 8 were incorrectly published. The correct figures, with their corresponding captions, are presented here.