Copper-Line Topology Impact on the Reliability of SiOCH Low- $k$ for the 45-nm Technology Node and Beyond

SiOCH low-k dielectrics introduction in copper interconnects associated to the critical dimensions reduction in sub-45-nm node technologies is a challenge for reliability engineers. Circuit wear-out linked to low-
k
dielectric breakdown is now becoming a major concern. With line-to-line spacing reduction, the control of the line shape and of the spacing uniformity within a wafer is becoming first-order parameters governing the low-
k
dielectric reliability. Improving the low-
k
reliability requires to discriminate each topological effect and to quantify its impact on the lifetime at product level. This paper demonstrates that the copper line shape induces a preferential breakdown of the dielectric close to the SiOCH/SiCN capping even at nominal voltage. The impact of the line edge roughness is studied with the introduction of a simple analytical model. Moreover, the impact of the roughness on the product lifetime has been quantified. It is demonstrated that the line-to-line spacing variation is less critical at the operational voltage than at high voltage stress. Finally, the impact of the spacing uniformity within the wafer and from wafer to wafer (reflecting the spacing fluctuation from product to product) on the Weibull shape is quantified and reported to be voltage-dependent in agreement with the experimental detail.