A CMOS single chip receiver with RF front-end and baseband processor for Band-III T-DMB/DAB applications

This paper describes a fully integrated CMOS single chip receiver for Band-III T-DMB/DAB applications, which is composed of RF front-end, the 10-bit analog-to-digital converter (ADC), and digital signal processing part. The RF front-end part is implemented with low-IF architecture and most of building blocks such as low noise amplifier (LNA), mixers, variable gain amplifiers (VGA), channel filter, phase locked loop (PLL), voltage controlled oscillator (VCO) and the PLL loop filter are integrated. The ADC is implemented with pipeline architecture, the number of bits of 10-bit and operates at 8.192 MHz. And the digital signal processing part is composed of baseband processor, audio and video (AV) decoder. And it manipulates the received T-DMB data stream. The RF front-end and ADC parts are implemented using full custom design and the baseband processor is designed using a CMOS standard-cell library. The single chip receiver for T-DMB/DAB systems is fabricated in a 0.18um mixed signal CMOS process. The sensitivity of the single chip is -87 dBm over the Band-III (174–239 MHz) frequency. The overall power consumption is about 254 mW (RF front-end: 54 mW, ADC: 10 mW, baseband processor: 70 mW and A/V decoder: 120 mW) at supply voltage of 1.8V/3.3 V. The chip area is 7.9 × 7.9 mm
²
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