An FPGA-based Space-time coded telemetry receiver

The significant problem of data dropouts in aeronautical telemetry due to multiple transmit antennas has escalated as transmit data rates have increased. A proposed solution of using a space-time coded signal can resolve these data dropouts at the expense of increased receiver complexity. This paper describes an implementation overview of an FPGA-based space-time coded telemetry receiver and the various challenges associated with its realization. In addition, we discuss the productivity of the high-level design tool used in constructing the receiver, Xilinx system generator for DSP. With some overhead in terms of FPGA fabric usage and clock speed, our estimates show a 2 - 3x productivity improvement over standard HDLs.