Optimization of n-channel tunnel FET for the sub-22nm gate length regime

In this work we explore for the first time, the design space for n-channel T-FETs with gate lengths below 22 nm using extensive device simulations. We show that the heterojunction tunnel-FET can satisfy ITRS requirements for HP and LSTP can be achieved using a SiGe-source device by an optimum choice of gate dielectric thickness and Ge fraction in Si
_1-gamma
Ge
_gamma
.