Good 150°C retention and fast erase characteristics in charge-trap-engineered memory having a scaled Si3N4 layer

We report a new charge-trap-engineered flash non-volatile memory that has combined 5nm Si
3
N
4
and 0.9nm EOT HfON trapping layers, within double-barrier and double-tunnel layers. At 150°C under a 100μs and ±16V P/E, this device showed good device integrity of a 5.6V initial ΔV
th
window and 3.8V 10-year extrapolated retention window. These data are better than the 3.3V initial ΔV
th
and 1.7V 10-year data for a similar structure not having the extra HfON layer.