Device and reliability improvement of HfSiON+LaOx/metal gate stacks for 22nm node application

For the first time, we illustrate the importance of process sequence for LaOx capped HfSiON/metal gate on performance, variability, scaling, interface quality and reliability. La diffusion to the high-k/low-k interface controls V
t
, as well as strongly affects mobility, N
it
and BTI. La diffusion is limited to the Si surface by employing SiON interface layer (IL) mitigating the issues of La-induced mobility degradation and PBTI. Improved V
t
tunability, reliability and performance are achieved with optimized process sequence, high-k thickness control, LaOx deposition and SiON (not SiO
2
) IL. T
inv
=1.15nm and V
t,lin
=0.31V was obtained while achieving the following attributes: mobility∼70%, N
it
≪5×10
¹⁰
cm
⁻²
, ΔV
t
≪30mV within wafer, BTI ΔV
t
≪40mV at 125°C. By optimizing these gate stack factors, we have developed and demonstrated structures for 22nm node LOP application.