A low-jitter 1.5-GHz and large-EMI reduction 10-dBm spread-spectrum clock generator for serial-ATA

A low-jitter and large-EMI-reduction spread spectrum clock generator (SSCG) for Serial-ATA (SATA) was developed. A low-jitter voltage-controlled oscillator (VCO) with a high-frequency limiter was developed to prevent the SSCG from malfunctioning. This VCO achieved far less jitter than that of a conventional VCO. An autocalibration technique suitable for this VCO was developed to prevent the SSCG from degrading performance because of process variations. A SATA PHY using a technique for calibrating the SSCG was developed to use an inexpensive but large frequency-variation reference oscillator. This technique was used to calibrate the SSCG output-signal frequency. This is achieved by shifting an SSCG divide ratio by utilizing the difference between an SSCG output signal frequency and a received signal frequency. These techniques were fabricated in 0.13- and 0.15-mum CMOS processes. The proposed SSCG achieved a 10.0-dB reduction in EMI. The variation in the rms jitter at 1.5 GHz with spread-spectrum clocking was reduced from 2.1-7.8 ps to 1.9-3.3 ps by the proposed autocalibration technique. The proposed SATA PHY achieved less than 400-ppm production-frequency tolerance of reference clocks.