Repeatability and Stress Level Dependence on ESD-CDM Testing for Microelectronic Components

The effect of CDM stress tests with pulse repetition has been investigated including the relation between discharge energy and first peak current. The dependence of capacitance and package size on peak current has also been studied. The larger the capacitance, the higher the peak discharge current and the greater the discharge energy. The peak current also increases with package area and saturates at the device with package area over 250 mm². The standard CDM testing usually provides three-pulse positive and negative testing to verify the ESD-withstand voltage of a product for reliability testing. This voltage typically relates to internal factors such as product capacitance, protection circuit design and technology. However, pulse repetition and stress level also affect the ESD sensitivity of a device. The comparison between CDM-withstand stress level and repeatability of memory products is presented. The withstand voltage of a product is 1000 V with 1+/- stress pulse, whereas it is 750 V with 3+/- stress pulses and 500 V with 10+/- stress pulses. The CDM-withstand level decreases with stress pulse repetition. The electrical test yield of memory product after CDM stress test is reported. It is proposed that not only stress level but also the repetition of the testing pulse influence an electrical test yield.