Investigation of GIDL current Injection Disturb Mechanism in two-transistor-eNVM memory devices

A programming disturb mechanism in the uniform channel program and erase (UCPE) eFlash 2TC (two transistor cell) is investigated. High GIDL current from the SG (selected gate) on the selected row and unselected columns introduce additional gate disturbs in a high density eFlash product. It is observed that the 1TC eFlash without an SG configuration did not show the same mechanism. When the SG bias is optimized, the yield was maximized. The higher SG bias can result in an SG turn-on driven gate disturb and the lower SG bias can result in a GIDL driven disturb. The flash p-well bias was also optimized not only for program Vt window but GIDL current because of excessive substrate injection with a high junction field. These leaky bits can impact the overall yield. Optimizing the S/D junction profiles with Vt adjustment successfully suppressed the hot carrier injection induced disturb.