Analysis of snubber-clamped diode-string mixed voltage interface ESD protection network for advanced microprocessors

A novel snubber-clamped diode-string ESD protection circuit for mixed voltage interface microprocessor applications is described. Analytical models, circuit simulation, electrical characterization, ESD electrothermal simulation, ESD test data, and an ESD analytical failure model are shown for shallow trench isolation (STI) and LOCOS CMOS technologies.