Low power ASIC design for wireless communications

This paper details a design path for the conversion of high level, signal processing block diagrams to ASIC design, using VHDL. A transceiver module for wireless serial communication between multiple terminals was designed as an ASIC using Signal Processing Worksystem (SPW) and Synopsys. Mobile communications systems require compact, low power components to reduce their size and weight. The transceiver connects with passive devices, so it must incorporate control functions to interact smoothly with other devices. SPW was used to design the controller in order to investigate the possibility of ASIC design from this level. The high level block diagram was converted to VHDL using a tool supplied by SPW. To complete the design the code generated by SPW was passed to the Synopsys VLSI design tool, where it is compiled as an ASIC.