Intermediate digital chip sensor for the EUDET-JRA1 high resolution beam telescope

A high resolution beam telescope, based on CMOS Monolithic Active Pixels Sensors (MAPS), is being developed within the EUDET collaboration, a coordinated detector R&D program for a future international linear collider. A very good spatial resolution ≪ 5 μm, a fast readout time of 100 μs for whole array and a high granularity can be obtained with this technology. A recent fast MAPS chip, designed on AMS CMOS 0.35 μm Opto process and called MIMOSA22, was submitted to foundry in October 2007. MIMOSA22 has an active area of 26.5 mm
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with a pixel pitch of 18.4 μm arranged in an array of 576 rows by 136 columns where 8 columns have analog test outputs and 128 have their outputs connected to offset compensated discriminator stages. The pixel array is divided in seventeen blocks of pixels, with different amplification gain, diode size, pixel architecture and is addressed row-wise through a serially programmable (JTAG) sequencer. The sequencer operates as a pattern generator which delivers control signals both to the pixels and to the column-level discriminators. Discriminators have a common adjustable threshold, with internal DAC, controlled by the JTAG. MIMOSA22 is the last chip (IDC-Intermediate Digital Chip), before the final sensor of the EUDET-JRA1 beam telescope, which will be installed at the 6 GeV electron beam line at DESY in spring 2009. In this paper, laboratory tests results on analog and digital parts are presented. For this purpose, a
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Fe source is used for calibration of pixels. Test beam results, obtained with a 120 GeV pions beam at CERN in summer 2008, are also presented. In the last part of the paper, a new chip MIMOSA22-bis, with radiation tolerant pixel architectures (evolution of MIMOSA22) will be discussed.