A 20GS/s 8-Bit Current Steering DAC in 0.25μm SiGe BiCMOS Technology

This paper presents the design of an 8-bit 20 GS/s DAC. The DAC is implemented with a modified current steering architecture where unlike the conventional binary weighted architecture a R-2R ladder DAC architecture is used as the LSB sub-DAC. In simulation the 8-bit DAC shows 7.83 ENOB for 9 GHz of input sinusoidal at 20 GHz of sampling rate with the power dissipation of 2.5 W. The measurement results of the 4-bit LSB sub-DAC show that the sub-DAC can work up to 30 GHz with a power dissipation of 455 mW.