A wide band voltage mode sense amplifier receiver for high speed interconnects

In this paper, a novel architecture is proposed for a voltage mode sense amplifier in the receiver for high speed interconnects. This is designed with the objective of achieving higher speed and wider bandwidth than those already reported in the literature. In the conventional voltage mode sense amplifier, the drains of the input transistors are connected to the sense nodes of the cross coupled inverters. In the proposed voltage mode sense amplifier, the drain of the input transistors are directly connected to the output of cross coupled inverters. This reduces the number of series transistors in the evaluation path and hence it reduces the switching times. Effectiveness of this technique is studied through simulation with Synopsys HSPICE using 180 nm technology models. The results obtained are compared with those obtained using the conventional voltage mode sense amplifier and also with that obtained using current mode sense amplifier. From the simulation results, it is found that the proposed voltage mode sense amplifier has a bandwidth which is twice that of conventional voltage mode sense amplifier. Current mode sense amplifier dissipates about six times more power than the proposed voltage mode sense amplifier to achieve identical bandwidth and delay. The proposed amplifier has a bandwidth of 11.6 GHz and a delay of 20 ps in 0.18 mum technology.