Quad-level bit-stream signal processing on FPGAs

Quad-level bit-stream signal processing (BSSP) circuits are implemented and their performances are compared with previously published tri-level and bi-level BSSP implementations on FPGAs. BSSP refers to the process of performing computation directly on over-sampled delta-sigma modulated signals to eliminate the need of resource consuming decimators and interpolators. Quad-level BSSP offers better performance than their bi-and tri-level counterparts at the expense of higher resource utilization. Using a digital phase locked loop (DPLL) and a quadrature phase-shift keying (QPSK) demodulator as application examples, the effectiveness of quad-level BSSP on FPGAs is studied. The BSSP approach will be contrasted with conventional multi-bit implementations using built-in digital signal processing blocks in modern FPGAs.