Experimental verification and analysis for noise isolation of analog and digital chip-package-PCB hierarchical power distribution network

This paper presents and verifies a co-modeling and investigation approach of noise isolation analysis in hierarchical power distribution network (PDN) for low-noise 3D system-in-package (SiP) design. It is based on a hierarchical modeling to combine the lumped circuit models at both on-chip level PDN and off-chip level PDN. The proposed hierarchical PDN model was successfully validated with good correlations and subsequent analysis to a series of Z
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PDN impedance measurements with a frequency range from 1MHz to 3GHz. Using the proposed model, we can analyze and estimate the performance of the chip-package-PCB hierarchical PDN as well as can predict the effect of high frequency electromagnetic interactions between the on-chip level PDN and the off-chip level PDN.