ILP platform optimization of a YAPI parallel H.264/AVC encoder

The H.264/AVC (Advanced Video Codec) new video coding standard provides higher coding efficiency relative to former standards at the expense of higher computational requirements. Given the potential applications of this technology, we are developing an application environment able to decode an MPEG2 stream, convert it into an H.264 stream, and stream it over a network. This paper focuses on the H.264 video encoder implementation. The absolute complexity of the obtained cost-efficient configuration outlined the potential of using a multiple processors platform for executing a parallel code version of the H.264 reference software. For this, a starting YAPI parallel Kahn Process Network (KPN) model is proposed. This model has been implemented and validated at a high system-level using the YAPI multi-threading programming interface. To identify the potential bottlenecks of the starting parallel model, communication and computation workload analysis are considered. Based on this analysis, an optimized parallel YAPI/KPN model with maximum workload balance is provided. For cost-effective realization, mapping the validated parallel model on the STMicroelectronics mb392 multiprocessor platform is motivated. For this purpose, a static code parser for the ST220 Very Large Instruction Word (VLIW) processor is developed to analyze, for each process of the model, the instruction level parallelism (ILP) effectively used by the ST220 cross compiler. Using this tool, the binary code of each process, cross-compiled for an ST220, is statically analyzed and the processes demanding further low level optimization are identified. To maximize the ILP for the ST220 VLIW architecture, a low-level algorithmic optimization of the motion estimation and compensation process is performed.