40-Gb/s two-parallel Reed-Solomon based Forward Error Correction architecture for optical communications

This paper presents a high-speed forward error correction (FEC) architecture based on two-parallel Reed-Solomon (RS) decoder for 40-Gb/s optical communication systems. A high-speed two-parallel RS(255,239) decoder has been designed and the derived structure can also be applied to implement the 40-Gb/s RS FEC architecture. The proposed 40-Gb/s RS FEC has been implemented with 0.18-mum CMOS standard cell technology in a supply voltage of 1.8 V and Xilinx Virtex4 FPGA. The implementation results show that 16-Ch. RS-based FEC architecture can operate at a clock frequency of 160 MHz and has a throughput of 41 Gb/s for the Xilinx Virtex4 FPGA. Also RS-based FEC operates at a clock frequency of 400 MHz and has a throughput of 102-Gb/s for 0.18-mum CMOS technology.