Timing and carrier recovery techniques in DSP based digital receivers

In conventional receivers, carrier recovery and timing recovery are performed in the analog domain by controlling the frequency and phase of voltage controlled oscillators (VCO) in their respective phase locked loop (PLL). When the control signal for these loops are generated in the sampled data domain by DSP techniques the digital samples must be brought to the analog domain by a pair of digital-to-analog converters (DAC). It is more cost effective to perform the entire signal processing function of the PLL in the digital domain and avoid the cost of the DAC and analog smoothing filter in the processing loops. In the full DSP implementation the receiver performs an initial complex down conversion with an asynchronous local oscillator set to the nominal final conversion frequency and then absorbs the residual carrier and phase uncertainty by data dependent control of a digital complex rotator. In a similar fashion sample timing is performed by the sampling the input signal with an asynchronous sampling clock operating at nominally twice the symbol rate and then absorbs residual frequency and phase of the sampling clock by resampling the data with a polyphase filter bank.<
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