VLSI architecture for a flexible block matching processor

A flexible and powerful VLSI architecture for the implementation of a wide spectrum of full search and reduced complexity search block matching algorithms is presented. Optimized efficiency for variable algorithm parameters is obtained by using a quadratic systolic array architecture with global accumulation, combined with a flexible meander-like data flow. Flexibility is further increased by cascadability and/or the possibility of parallel operation. Hardware overhead for particular algorithmic requirements, such as variable pixel resolution, subsampling with offset, and subpixel accuracy, is discussed in detail. A full-custom (CMOS) implementation for the architecture is described.<
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