Lithography friendly routing: From construct-by-correction to correct-by-construction

Deep sub-wavelength lithography, i.e., using the 193nm lithography to print 45nm, 32nm, and possibly 22nm integrated circuits, is one of the most fundamental limitations for the continuous CMOS scaling. Lithography printability is strongly layout dependent, thus routing plays an important role in addressing the overall circuit manufacturability and product yield since it is the last major physical design step before tapeout. This paper will discuss some recent advancement of lithography friendly routing from post-routing hotspot fixing (construct-by-correction) to during-routing hotspot avoidance (correct-byconstruction) guided by various lithography metrics. We will compare these approaches, and show how to combine them. We will also discuss the emerging research needs in lithography friendly routing, such as double patterning lithography and next-generation-lithography.