Low power design and implementation for a SoC

A set of SoC low power design methods is presented based system level, IP module level and gate level. These methods were applied to low power design of a SoC. The SoC power simulation results showed that the static and dynamic power of this SoC was quite low. The goals of the low power design methods applied on the design were achieved. The SoC has been implemented in 0.18 ¿m COMS process, the area is 8 × 8 mm², the operation frequency is 80 MHz and the power dissipation is about 454.268 mW.