A low power dynamic pseudo random bit generator for test pattern generation

Pseudo random bit generator is widely used in BIST for test pattern generation. Typical pseudo random bit generator adopts linear feedback shift register (LFSR) as its basic circuit. Dynamic LFSR (DLFSR[1]) which has better cryptographic properties with respect to typical LFSR consumes more power. This paper forwards a low power DLFSR (LDLFSR) circuit which achieves comparable performance with less power consumption. Typical LFSR, a DFLSR[1], a LDLFSR are compared on randomness property and inviolability property. Multi-layer perceptron neural networks are used to test these LFSRs¿ inviolability property. Result shows that LDLFSR keeps comparable performance with a 7% power reduction and a 5.6% area reduction.