A Low Complexity VLSI Architecture for Reed-Solomon Decoder

Reed-Solomon (RS) codes have been widely used in a variety of communication systems to protect digital data against errors or to reduce the signal to noise ratio requirement in transmission process. This paper presents an area-efficient 8-error correcting RS (255,239) decoder architecture using RiBM algorithm, implemented on a 0.25-¿m CMOS technology with a supply voltage of 2.75 V. The total number of gates is about 12,600, which illustrates about an order of magnitude reduction compared to existing RS decoders. This improvement in hardware complexity is due to using a low complexity multiplier over GF (28) and constant multipliers. The decoder has a data processing rate of 1.6 Gbits/s at a clock frequency of 200 MHz.