Multi-stage Pipelining MD5 Implementations on FPGA with Data Forwarding

This paper describes 3-stage and 4-stage pipeline MD5 implementations on FPGA. This work removes the data dependency of a single step inside the main loop of the MD5 algorithm by data forwarding methodology, and breaks that single step computation into 3/4 pipeline stages. Three implementations on Xilinx Vertex-II are given with the throughput get to 1.04 Gbps, and occupy 1064 hardware slices. Thus, the implementations achieve good tradeoff between hardware size and throughput in comparison with others.