A dedicated data flow architecture for hardware compilation

A dedicated data-flow architecture that has been designed to be a part of a hardware compiler is described. This machine evaluates attribute grammars in a data-flow fashion by accepting their reverse-dependency graph, which is similar to a data-flow graph. The outputs and the results of these evaluations are sent to the other components for later use. The machine is believed to be the first dedicated data-flow architecture suggested for this purpose. It takes advantage of parallelism at two levels: first, the components of the machine are organized in a pipeline fashion and can run concurrently; second, the execution of the instructions is done in parallel as well.<
>