10-bit 100MS/s CMOS pipelined A/D converter with 0.59pJ/conversion-step

A 31 mW, 10-bit 100 MS/s pipelined ADC has been developed. The proposed ADC achieves low power consumption, high noise immunity, and small area by employing a new opamp sharing technique that switches the summing node in an MDAC and a current source with a PVT condition detector. The ADC shows a DNL of less than 0.48 LSB and an INL of less than 0.95 LSB. Also, a SNDR of 56.2 dB is measured with a 1 MHz input frequency. It has been implemented in a 0.18 um CMOS process and it occupies 1.6 x 0.8 mm
²
of active area.