An 8mW 10b 50MS/s pipelined ADC using 25dB opamp

In 10-bit 50MS/s pipelined ADC is presented. A 25dB open loop dc gain amplifier is employed in the MDAC operation. The low opamp dc gain in the extreme is tolerated due to the use of a reference scaling scheme in conjunction with a background offset calibration. An intermediate gain stage is inserted into the pipeline to compensate for the accumulated reduction of reference and signal swing. The prototype IC implemented in a 90nm CMOS process achieves −63.2dB THD, 48.8dB SNR, and 48.6dB SNDR, while consuming 8mW from a 1V supply.