Predictability of program execution times on superscalar pipelined architectures

Predicting the execution time of straight line code sequences is essential for reliable real-time systems. Traditional timing techniques suck as table lookup method, instruction counting and averaging are inadequate to predict a tight execution time on reduced instruction set processors since they do not account for the low-level parallelism that exists in these processors. This paper presents a server based methodology for predicting point-to-point execution times of code segments. A sequence of assembler instructions is analyzed to identify the execution paths and the basic blocks within the execution path. The execution of these assembler instructions is simulated by scheduling them on the different servers such as caches and pipelines. Performance is predicted by consolidating the execution times of the basic blocks and then the execution paths. This methodology was applied to Alpha AXP architecture as a case study. Execution times of three benchmark programs were observed on an Alpha AXP machine and predicted using this methodology. The worst case time predicted by this methodology bounds the observed worst case time and the best case execution time is lower than the observed best case execution time.<
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