A Model for Predicting On-Current Degradation Caused by Drain-Avalanche Hot Carriers in Low-Temperature Polysilicon Thin-Film Transistors

A model for predicting on-current degradation caused by drain-avalanche hot carriers in NMOS low-temperature polysilicon thin-film transistors (TFTs) is described. The amount of trapped charge caused by hot-carrier stress was estimated by using a model describing the lightly doped drain region as an imaginary TFT, and it was found that the amount of trapped charge saturates as voltage-stress time passes. Moreover, the on-resistance increase caused by the trapped charge could be expressed as a function of voltage-stress time (t) , stress drain current (I
_{d_str}
), and stress drain voltage (V
_{d_str}
), i.e., DeltaR
_on
= I
_{d_str}
exp(-beta/ V
_{d_str}
) At
^B
. This function can be used to predict the on-current degradation of TFTs after a long time for various gate lengths, operation voltages, and crystallinities of polysilicon.