Test pattern generation for worst-case crosstalk faults in DSM chips using Genetic Algorithm

Nowadays, aggressive scaling of transistor dimensions has led to the reduction of process geometries and thereby higher device density in DSM chips. Higher signal switching speeds and increased aspect ratios of interconnects in chips has enforced the attention towards non conventional faults due to the coupling noise between adjacent interconnects. Crosstalk is one such major Signal Integrity issue, that can occur intermittently or permanently, which may lead to functional problems and even occasionally for failure of the chip. Testing the chips for such faults is essential even after manufacturing with certain design constraints to ensure the quality of the chip. Predetermined test patterns are necessary for testing such crosstalk related faults. In this paper, an elitist genetic algorithm has been developed to determine the test patterns for worst-case crosstalk faults. Fitness functions for all basic gates also based on the level of the gates have been developed. The algorithm was performed on some benchmark circuits and the determined test patterns were also verified.