Comprehensive study of S/D engineering for 32 nm node CMOS in direct silicon bonded (DSB) technology

This paper describes the fabrication process and device performance of CMOSFET with direct silicon bonded (DSB) substrate. This works offers the first comprehensive evaluation of source/drain engineering for DSB devices. Scanning spreading resistance microscopy (SSRM) technique reveals specific dopant profile that lateral diffusion along the bonding interface, in addition to the highly activated dopant at bonding interface in pMOSFET with DSB substrate. Key process condition, such as DSB thickness, hybrid formation process, source/drain engineering and optimization method are described.