Silicon on thin BOX (SOTB) CMOS for ultralow standby power with forward-biasing performance booster

Ultralow off-current (I
_off
les 1 pA/mum) ldquosilicon on thin BOX (SOTB)rdquo CMOSFETs were fabricated in 65-nm technology. Gate-induced drain leakage (GIDL) was adequately reduced by controlling the gate-overlap length with an additional offset spacer. Small threshold-voltage (V
_th
) variation under a wide-range back-gate-bias (V
_bg
) condition and suppressed I
_off
variation by V
_bg
control were demonstrated. Faster inverter delay (tau
_pd
) than conventional low-standby-power (LSTP) bulk CMOS was also achieved.