Design of Multiphase Decimation Filter IP Core in Software Radio Receiver

This thesis introduces the design of multiphase decimation filter IP core in software radio receiver in detail. This soft-core could automatically generate Verilog-HDL code with optimized-structure according to input parameters. The application of this core can decrease the design time and cost, and improve reliability; it can also be combined with the dynamic reconfiguration FPGA technology to realize the aim that real-time changing filter performance in order to satisfy the flexible demand of software radio application system.