Differential ECL/CML Synthesis for SiGe BiCMOS

A novel SiGe ECL/CML design flow is presented for the first time. It provides CMOS-style synthesis with differential SiGe BiCMOS ECL standard cells. A first version works in a 95 GHz one-mask HBT technology up to about 10 GHz clock rate. A synthesized CML/ECL FIFO buffer example with 497 ECL gates works up to 3 GHz data rate.