Compensation of systematic variations through optimal biasing of SRAM wordlines

Increasing process variability is slowing SRAM scaling by reducing both read and write margins. Existing techniques to compensate for systematic variations optimize cell stability with excessive penalty to writeability. To maximize overall yield, a sensor circuit is presented that optimizes the read / write tradeoff in the presence of process, voltage, and temperature variations. Sensors implemented in a low-power 45nm test chip adjust the wordline voltage to track changes in the optimal value within 30mV over the entire range of operation.