Scheduling in Performance Test environment

Nowadays automatic testing is getting more and more important in the telecommunication world. The sooner a fault is discovered the cheaper it is to correct it. If a fault is discovered during the development process the cost of the correction is significantly smaller. There are different test strategies, with different approaches like, conformance test, system test and performance test. The system test takes place after a successful conformance test. Performance test is analyzing the load characteristics of the system under test (SUT). In this article we describe the main attributes of performance testing, where the main challenge is to generate the expected load without having as complex hardware as the SUT is itself. Most of the papers, presented in this subject are focusing on the characteristics of the generated load, but not the way how to achieve it. These papers usually have the assumption that the load can be generated by deploying more hardware resources. Other papers propose new extensions for test description languages such SDL or TTCN-3. In this article we intend to describe a finite state machine (FSM) based model and an algorithm which improves the efficiency of scheduling in this performance test environment. We present an architecture based on the so called virtual threads, an algorithm to optimize the scheduling between these threads, and an example to demonstrate the algorithm.