Systematic design space exploration for customisable multi-processor architectures

A systematic approach to design space exploration of customisable options for multi-processor architectures is presented. This approach is used to explore a parameterisable system model as a part of a novel exploration tool. Architecture trends are analysed through the variation of prefabrication choice of number of processing elements (PEs) and cache size. Of note, is the relationship between multi-threading and off-chip memory access. This is shown to reduce performance by up to five times for a decimation case study. From the analysis of architecture trends, a post-fabrication choice of processing pattern is shown to provide up to three times improvement for a negligible area cost. In verification, the system model mimics the performance of sample graphics processors. This is achieved with a run time of only five minutes for a decimation case study with a model setup of eight processing elements and 16 KB cache.