Delay optimization of digital CMOS VLSI circuits by transistor reordering

In this paper the effects of transistor reordering on the delay of CMOS digital circuits are investigated, and an efficient method which uses transistor reordering for the delay optimization of CMOS circuits is presented. The proposed technique achieves significant reduction in propagation delays with little effect on layout area and power dissipation. The technique can be coupled with transistor sizing to achieve the desired improvement in circuit delay. Experimental results for benchmark circuits are given in 2.0, 1.2, and 0.8 /spl mu/m CMOS technologies. The average improvement in delay for the 20 benchmarks used in this paper is 9.1%.<
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