Autonomous gain verification algorithm for a dual mode digital hearing aid chip

A dual mode digital hearing aid chip with real-time autonomous gain verifications algorithm is proposed and implemented. Four proposed gain models due to the different internal sound paths are analyzed to verify its usefulness. By adopting this algorithm, a real-ear aided gain and a real-ear occluded gain which considers internal vent effect and leakage path effect are compared with conventional models. To evaluate this algorithm the implemented chip adopts two different modes; a hearing aid mode and a gain verification mode for a hearing aid operation and internal gain verification, respectively. The minimum and maximum convergence time of the presented algorithm covers 0.05 s at a 1 kHz input signal and 1.6 s at a 7.5 kHz input signal, respectively. The implemented chip dissipates less than 130 μW at a supply voltage of 0.9 V and occupies a 5.4 mm
²
core are at a 0.18 μm CMOS technology.