Extending SystemC clocks to model SoC

SystemC provides a clock with a limited interface. While it is generally not an issue for the modeling or the verification of a single IP, this limited API can hardly help modeling a large SoC using multiple dynamic clocks for power reasons. The SystemC clock is implemented with using the global timed event queue of the simulation kernel which can become a bottleneck of the simulation. Poor clock performances are thus discouraging using them like in OSCI/TLM models, but at the expense of complex timing management. This paper presents an extended clock API which also provides a scalable timing mechanism for the modules so that they donpsilat need to be aware of the clock period. These clocks both improve the simulation speed and ease the modeling while preserving ascending compatibility.