Minimization of CTS of k-CNOT Circuits for SSF and MSF Model

In this paper, we consider the problem of testing reversible circuits for a particular fault model: Stuck-at Fault Model. We propose a design-for-test construction technique for k-CNOT circuit having k ges 1 and only 2 test vector (i.e. minimal) suffice as their complete test set. We have also shown the way to exploit our method for the case of 0-CNOT circuits. Finally we provide some experimental results for the proposed method and compare it with existing method to show how the proposed one outperforms the existing one both in terms of number of test vectors of complete test set and number of gates need to be replaced in the design-for-test.