Analysis and Design of RF CMOS Attenuators

Attenuators are analyzed for their minimum Insertion Loss (IL), maximum attenuation and source-load matching performance. These results are used to make trade-offs in the design of a CMOS attenuator with wide dynamic range, designed and fabricated in a 0.13 $\mu{\hbox{m}}$ CMOS process. The design employs two non-identical cascaded T-stages that are activated consecutively to improve linearity. The design operates in the frequency band of DC-2.5GHz with 0.9–3.5 dB insertion loss and 42 dB maximum attenuation in the entire frequency range. Worst case S11 is ${- }\hbox{8.2~dB}$ across the frequency band. The design achieves an IIP3 of ${+ }\hbox{20~dBm}$ at mid-attenuation.